Conventional electropolishing (EP) is a common metal finishing process in which the metal object to be polished (the “work-piece”) is connected to the positive terminal of a DC electrical power supply as the anode. The surface of the work-piece or some portion of that surface is brought into contact with an electrolyte solution which, in turn, also contacts a second electrode (the cathode) which is connected to the negative terminal of the power supply. When a suitable voltage difference is applied between the two electrodes, or a suitable current density is established at the anode, then the work-piece undergoes anodic oxidation forming solvated metal ions that dissolve into the electrolyte. Within a certain range of operating conditions this occurs in such a way that rough areas of the surface become smoother (current density is defined as the electrical current per unit surface area of anode in contact with the electrolyte and has units such as mA/cm2).
EP is capable of producing a mirror-like reflective finish on many different kinds of metals and is especially useful for polishing metal parts with curved surfaces and complicated shapes. As described by D. E. Ward (pp. 100-120 in Electroplating Engineering Handbook, 4th Edition, L. J. Durney, Ed., Van Nostrand Co., NY, 1984), the optimum electrolyte composition and current density varies with the composition of the work-piece. The rate of the EP process is limited by mass transport of molecules and/or ions in the electrolyte close to the anode surface and is generally optimized by convection of the electrolyte.
Recent interest has focused on the use of EP to selectively remove excess copper in the fabrication of integrated circuits via the copper damascene process. In a typical copper damascene process, a silicon wafer is uniformly covered with a dielectric layer, for example ˜0.5 microns of SiO2. A pattern corresponding to the conductive circuit elements is then etched through the dielectric layer by photo-lithographic methods, and the entire surface is coated with a thin “barrier” layer, for example <10 nm tantalum or tantalum nitride. A layer of copper is then grown over the entire surface of the wafer by means of electroplating. This copper “blanket” must be sufficiently thick to fill the etched circuit features (˜0.5 microns), but is generally not thicker than about 1 micron in total thickness. The external surface of the copper blanket generally retains topographic features that conform to the larger features in the underlying etched pattern. The next step in the process requires removing all excess copper from the surface of the barrier-coated dielectric while leaving the etched circuit elements filled with copper. In addition, the final surface must be left planar to within very narrow tolerances in order to permit subsequent fabrication of addition layers of circuitry. The cross-section of a typical copper damascene wafer before and after polishing/planarization is shown schematically in FIG. 1.
Many different processes are capable of chemically or mechanically removing material from the surface of a metal work-piece, but such processes differ in their ability to polish or planarize, that is to reduce the roughness of the surface. By planarization is meant the ability to preferentially remove topographic high points (plateaus or ridges) of both large and small lateral dimensions so that the polished surface progressively approaches an ideal plane. Planarizing conventionally plated Cu damascene wafers requires especially high efficiency.
Planarization and removal of excess copper from Cu damascene wafers is currently achieved by means of chemical-mechanical polishing (CMP), involving mechanical abrasion and chemical reactions with oxidizers and other chemicals. However, CMP is a costly process, generates hazardous waste products, and is incompatible with the mechanically fragile materials currently under development for improved dielectric layers.
EP has been considered as an alternative to overcome the limitations CMP. Many different processes are capable of chemically or mechanically removing material from the surface of a metal work-piece, but such processes differ in their ability to polish or planarize, i.e., to reduce the roughness of the surface. By planarization is meant the ability to preferentially remove topographic high points (plateaus or ridges) of both large and small lateral dimensions so that the polished surface progressively approaches an ideal plane. Planarizing conventionally plated Cu damascene wafers requires especially high efficiency.
“Planarization efficiency” may be defined quantitatively by reference to FIG. 2. Consider a surface topography where the vertical distance between high points and low points is measured by amplitude “a,” the lateral distance between these points is represented by λ, and the average thickness of the work-piece is τ. The planarization efficiency of a polishing process is defined by the derivative da/dτ, namely the differential change in amplitude of a topographic feature with the change in average thickness. Depending upon the planarization mechanism da/dτ may vary with various processing conditions and with the magnitude of a and λ. Measurements of planarization efficiency are important for practical purposes and also useful for distinguishing different planarization mechanisms.
Planarizing conventionally plated Cu damascene wafers requires that initial topographic features, with initial amplitude ao˜0.5 microns and λ=10 to 100 microns, must ultimately be reduced to a <25 nm, while removing only ˜1-1.5 microns of material overall (Δτ=−1 micron). Conventional EP can be highly efficient at planarizing surface features where λ<1 micron, but is much less efficient for larger features (λ>10 micron). Thus use of EP to planarize Cu damascene wafers requires the use of additional technologies. For example, the SFP tool (ACM Research, Inc.) is only useful for polishing wafers which have been produced by a specialized “hump-free, dishing-free” plating process which minimized the initial topography. Similarly, in electromechanical polishing methods, the EP process is augmented with a more selective mechanical abrasion process.
Fundamental studies have shown that the rate and planarization efficiency of EP vary with a, λ, and with convective transport in the electrolyte solution. Electrolyte convection increases the rate of EP by enhancing mass transport of solubilizing molecules such as water to the surface of the work-piece (see for example S. H. Glarum, J. H. Marshall, J. Electrochem. Soc., 132, 2872 (1985)). More efficient mixing of the electrolyte produces a thinner convective boundary layer resulting in faster mass transport. C. Wagner (J. Electrochem. Soc., 101, 225 (1954)) showed that for “ . . . an ideal electropolishing process,” where the thickness of the convective boundary layer is greater than a and λ, the planarization efficiency is given by the relation: da/dπ=2πa/λ. However, when λ is larger than the convective boundary layer thickness, then da/dτ→0, and no planarization will occur. Accordingly, to planarize features with large λ by EP, the efficiency of convective mixing and rate must be restricted, and even in the “ideal” limit planarization efficiency decreases with increasing λ.
There remains a need for an EP process that is capable of planarizing in an efficient, low-waste manner the topographic features on semiconductor substrates, e.g., Cu damascene wafers produced by the current plating technology, which is advantageously capable of producing commercially acceptable products without the use of additional planarizing steps, means such as specialized plating technologies, masking, degrading polishing materials giving changing performance, and requiring frequent regeneration, or mechanical abrasion.